The continuing push to produce faster microelectronic devices with lower power consumption has resulted in the miniaturization of such devices. In particular, smaller gate length and channel lengths are conducive to the low voltage and faster operation of transistor devices, such as complementary metal oxide semiconductor (CMOS) transistors. However, with shrinking process geometries, a number of new design problems arise.
For instance, as gate dimensions are reduced, it has become necessary to adjust and better control the dimensions of the channel and doped regions of the substrate that are associated with the gate. This is necessary to prevent a number of short channel effects such as, threshold voltage variation, drain induced barrier lowering (DIBL), punch-through, leakage currents, hot carrier injection, and mobility degradation.
Consider, for instance, the dimensions of shallow junctions and pocket region structures. Shallow junctions, also referred to as source drain extensions, or light or medium-doped drain (LDD and MDD, respectively) regions, are implanted as extensions to the larger and more heavily doped source and drain regions, to reduce hot carrier injection-induced damage to gate dielectric layers and improve short channel effects. Hot carriers, electrons with higher than average energy, form because of the stronger electric fields produced in small transistor device geometries. Shallow junctions, implanted before sidewall formation and source and drain implantation, provide a doping gradient between the source and drain regions and the channel. The lowered electric field in the vicinity of the channel region of such devices reduces the formation of hot carriers.
Sub-0.1 micron transistor devices are also highly susceptible to leakage currents, or punch-through, when the transistor is off. These conditions can arise when the shallow junctions and the source/drains are not properly formed. Thus, leakage currents can be reduced if the shallow junctions are formed with well-defined boundaries, as exemplified by an abrupt decrease in dopant concentration, to support low-voltage operation of the transistor and to define the width of the channel region of the transistor.
Unfortunately, however, it can be very difficult to ascertain any irregularities in these shallow junctions or source/drain areas using standard imaging techniques. This is largely attributable to the fact that these shallow junctions do not show up in the cross section scans of an imaging tool, such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM). Thus, it can be very difficult to ascertain with any degree of certainty what structural defects or irregularities might exist in the junction or gate areas of the microelectronics device.
Accordingly, what is needed in the art is an improved method of obtaining an image of the junctions areas of a microelectronics device.